Electronic Circuit Arrangement for Processing Binary Input Values

ABSTRACT

Electronic circuit arrangement for processing binary input values xεX of a word width n (n&gt;1), with a first, second and third combinatory circuit components configured to process the binary input values x to form first, second and third binary output values. The arrangement further includes a majority voter element configured to receive the binary output values and provide a majority signal based on the received binary output values. The second and third combinatory circuit components are designed, as regards faults during processing of the binary input values x in the first combinatory circuit component, to process binary input values of a true non-empty partial quantity X 1  of the quantity of binary input values X in a fault-tolerant manner and process binary input values of a further non-empty partial quantity X 2  of the quantity of binary input values X different from the true non-empty partial quantity X 1  in a fault-intolerant manner.

The disclosure relates to the field of error correction in an electronic circuit.

BACKGROUND

The level of integration of electronic circuits has been increasing for many years. The dimensions of circuit elements such as transistors, the dimensions of connecting structures, current intensity and voltage values are forever getting smaller. As a result of this there has been a rise in error frequency.

It is known to make circuits or parts of a circuit fault-tolerant in respect of a multitude of faults by tripling the circuits. A circuit S is tripled to give three circuits S₁, S₂ and S₃, which are functionally equal to circuit S. The outputs of circuits S₁, S₂ and S₃ are connected to a voter V which performs a majority decision. System triplication also called TMR has been described, for example, in Barry W. Johnson “Designs and Analysis of Fault Tolerant Digital Systems”, Addison Wesley Publ. Comp. Reading, Ma., 1989, p. 51-53 and U.S. Pat. No. 6,963,217 B2. A random fault in one of the three partial systems S₁, S₂ and S₃, which for any given input value affects the output of one of circuits S₁, S₂ or S₃, is tolerated by a TMR system.

In practical applications it is sometimes merely necessary for the fault-tolerant system to behave especially reliably only for the input of certain defined values, whilst for other input values no such high reliability of output values is required. For example, a circuit for triggering an airbag in cars should produce the control signals for tripping the airbag with an especially high degree of reliability when inputting the corresponding tripping signal, whilst production of the control signals for opening and closing the central locking system is not subject to such a high reliability requirement.

The disadvantage with the known triplication of a system with voter is the fact that it requires a great deal of hardware, that energy consumption is more than three times as high in comparison to the original system and in that it is not possible to vary the reliability for different input values which from the start require different reliability levels.

SUMMARY

It is an object to propose an improved electronic circuit arrangement comprising a plurality of combinational circuit arrangements for processing binary input values in a fault-tolerant manner, which is realizable but costs less to produce.

An electronic circuit arrangement or device for processing binary input values according to independent claim 1 is provided. Advantageous embodiments are the subject of dependent sub-claims.

Due to the fault-tolerance for input values from a non-empty subset X₁ of all input values X and no fault tolerance for input values from a further non-empty subset X₂ of all input values X the expenditure for realising the circuit arrangement with respect of the known system triplication and the majority decision can be reduced. It is advantageous if the subset X₁ of the input values for which the circuit arrangement is to be fault-tolerant can be fixed in such a way that all necessary requirements as regards the fault tolerance of the circuit arrangement are met. Expenditure on hardware is less since the cost for implementation can be adapted to suit the necessary fault-tolerance.

A further development provides for the second and third combinational circuit components to be further designed to incorporate the following features:

-   -   in a fault-free case the second binary output value of the         second combinational circuit component and the third binary         output value of the third combinational circuit component are         equal to the first binary output value of the first         combinational circuit component, for all binary input values of         the non-empty proper subset X₁,     -   for all binary input values from the further non-empty subset X₂         the second binary output value of the second combinational         circuit component and the third binary output value of the third         combinational circuit component are non-equal, and     -   for all binary input values of the subset X₁ the following is         true     -   for each bit of the first combinational binary output value of         word width a1: at least the second binary output value of the         second combinational circuit arrangement or at least the third         binary output value of the third combinational circuit component         is equal to the first binary output value of the first         combinational circuit component.

With an advantageous design provision may be made for the second combinational circuit component to be configured so as to process the binary input values x such that the second binary output value is equal to the first binary output value.

One embodiment provides for further combinational circuit components each of which are configured to process the binary input values x to form the first binary output value, and the output of which is respectively connected to an input of the majority voter element. If, for example, two further circuit components are present which process binary input values to form the first binary output values, the fault tolerance for input values from the partial quantity X₁ is equal to the fault tolerance of a quintupled system with majority decision without requiring hardware expenditure for a quintupled system with majority decision.

A further development of the invention can provide further majority voter elements whose input for receiving the respective binary output value is connected with the output of all combinational circuit components and which are respectively configured, depending upon the received binary output values, to provide a majority signal at their output. In one design exactly two further majority voter elements are formed. This design enables faults to be tolerated also in a voter element.

With respect to a preferred embodiment, the respective input of all combinational circuit components is serial-connected with an output of a further circuit component, wherein the further circuit component is configured to process binary input values uεU to form binary output values W which, at least partially, are different from the binary input values xεX, wherein X₁⊂W. If certain input values of the combinational circuit components are produced with the aid of the serial connected further circuit not as output values, the circuit arrangement provided can realise the fault tolerance only for the actually present input values or for a subset of these input values. The values not occurring as output values of the further circuit provided need not be added to the quantity X₁, for which a fault tolerance is required, resulting in a reduction in expenditure for a realisation without the fault tolerance being diminished.

With an advantageous design provision is made for a further combinational circuit component configured to process the binary input values x to form binary control signals and a multiplexer element, wherein

-   -   the output of the further combinational circuit component         carrying the binary control signals is connected with the         control input of the multiplexer element,     -   a first data input of the multiplexer element is connected with         the output of the first combinational circuit component, and     -   a second data input of the multiplexer element is connected with         the output of the majority voter element.

In this design individual faults of the circuit component are tolerated especially advantageously.

A convenient further development may provide for the binary input values of non-empty subset X₁ to form a subset of binary input values, so that for a set Φ of faults φ₁, . . . , φ_(k) occurring in the first circuit component the following is true: S(x)≠S(φ,x) for xεX₁, wherein S(φ, x) is the binary output value of the first combinational circuit component, if fault φεΦ is present and the binary input value x is input. In this way the system can be secured against certain faults in critical areas.

One embodiment provides for X₂=(X\X₁).

In an advantageous design provision is made for the binary output value of the second circuit component to be 1 and for the binary output value of the third combinational circuit component to be 0 for the binary input values from the further non-empty subset X₂.

DESCRIPTION OF PREFERRED EMBODIMENTS

Embodiments will now be explained in more detail with reference to figures of the drawing, in which:

FIG. 1 is a schematic illustration of a known combinational circuit,

FIG. 2 is a schematic illustration of a known combinational circuit with triplification,

FIG. 3 is a schematic illustration of a combinational circuit according to one embodiment,

FIG. 4 is a schematic illustration of a combinational circuit according to the embodiment of FIG. 3 with a typical circuit implementation,

FIG. 5 is a schematic illustration of a combinational circuit according to a further embodiment,

FIG. 6 is a schematic illustration of a combinational circuit according to an embodiment with an additional circuit for generating a control signal and with a multiplexer element,

FIG. 7 is a schematic illustration of a combinational circuit according to an embodiment with further combinational circuit components,

FIG. 8 is a schematic illustration of a combinational circuit according to an embodiment with several voter elements,

FIG. 9 is a schematic illustration of a combinational circuit according to an embodiment with an upstream circuit element, and

FIG. 10 is a schematic illustration of a further combinational circuit.

FIG. 1 shows a known combinational circuit S 11, which for an input value x from an input set X outputs a value y=S(x), so that the circuit S 11 realises the function S(x). The word width of the input of S 11 is m and the word width of the output is n. Therein: m>1 and n≧1.

FIG. 2 shows, how according to the state of the art a fault-tolerant so-called TMR (Triple Modular Redundancy) system can be realised from S 11 with m>1 and n≧1 through system triplication and a voter.

The combinational circuit S 11 of FIG. 1 has been triplicated to form 3 combinational circuits S₁ 21, S₂ 22, S₃ 23. The three circuits S₁ 21, S₂ 22 and S₃ 23 realise the functions y₁=S₁(x), y₂=S₂(x) and y₃=S₃(x), which respectively equal the function y=S(x). Therefore it is true for all xεX that S₁(x)=S₂(x)=S₃(x)=S(x). The output with a width of n-bit of circuits S₁ 21, S₂ 22 and S₃ 23 are connected to three n-bit wide inputs of a voter V 24, which at its output outputs the n-bit wide signal y. For each bit of its n-bit wide inputs the voter outputs the value which occurs most frequently. If y₁=(y₁ ¹, . . . , y₁ ^(n)), y₂=(y₂ ¹, . . . , y₂ ^(n)), y₃=(y₃ ¹, . . . , y₃ ^(n)), y=(y¹, . . . , y^(n)), then for i=1, . . . , n the value of y^(i) is determined as y^(i)=(y₁ ^(i)

y₂ ^(i))

(y₁ ^(i)

y₃ ^(i))

(y₂ ^(i)

y₃ ^(i)). Voters with 3 or more inputs are known to the expert.

FIG. 3 shows a combinational circuit with a set X of possible input values, which is fault-tolerant for a true or proper subset X₁⊂X of its input values and whose realisation expenditure is less than a TMR realisation. In contrast to a TMR realisation according to the state of the art such as described in FIG. 2, where the combinational circuit S 11 has been replaced by three functionally equal circuits S₁ 21, S₂ 22, S₃ 23, the combinational circuit S 11 of FIG. 1 in the circuit according to the invention of FIG. 3 has been replaced by three circuits S₁ 31, s₂ 32 and s₃ 33, which are not all functionally identical. The circuits S₁ 31, s₂ 32 and s₃ 33 are also called the first, second and third combinational circuit component of the circuit arrangement according to the invention of FIG. 3. In there A₁ with A₁=n is the number of binary outputs of the first circuit component and a₁ is the number of binary outputs of the second and third circuit component, wherein a₁≦A₁. In order to illustrate the principle of the invention as clearly as possible, it is assumed for FIG. 3 that both S₁ 31 and s₂ 32 as well as s₃ 33 have only one binary output, so that the output word width a₁ is equal to 1. Circuit S₁ 31 realises the same function y=S₁(x)=S(x) as circuit S 11. Circuits s₂ 32 and s₃ 33 realise the functions y₂=s₂(x) and y₃=s₃(x), wherein for xεX₁: s₂(x)=s₃(x)=S₁(x).

Thus: if the input value x is from the first subset X₁ of X, then S₁ 31, s₂ 32 and s₃ 33, in the fault-free case, output the same values respectively. For xε(X\X₁) at least one of values s₂(x) or s₃(x) output by s₂ 32 or s₃ 33 is equal to S₁(x), which is formally expressed by (s₂(x)=S₁(x))

(s₃(x)=S₁(x)) for xε(X\X₁). There is a non-empty subset X₂ ⊂(X\X₁) of X\X₁ for which s₂(x)≠s₃(x) for xεX₂ and for xεX₂ only two and not all three of values S₁(x), s₂(x) and s₃(x) are equal. Thus for the input values x with xεX₁, as already mentioned: S₁(x)=s₂(x)=s₃(x).

For xεX₁ the circuit arrangement of FIG. 3 has the same fault tolerance characteristics as the circuit arrangement of FIG. 2, whilst the circuit arrangement of FIG. 3 for xεX₂ is not fault-tolerant. Due to the fact that fault tolerance is required only for certain input values and not for all xεX, the fault tolerance characteristics can be accurately adapted and circuit expenditure for the circuit arrangement in FIG. 3 is often surprisingly considerably reduced compared to the circuit expenditure in FIG. 2, which is advantageous.

In table 1 the truth table of a Boolean function S₁(x)=S₁(x₁, x₂, x₃) is shown, which shall be realised by a fault-tolerant circuit arrangement according to FIG. 3. y=S₁(x), x₁, x₂ and x₃ are binary variables.

TABLE 1 x₁ x₂ x₃ S₁(x) X₁ 0 0 0 0 + 0 0 1 1 + 0 1 0 0 0 1 1 1 + 1 0 0 1 1 0 1 0 1 1 0 1 1 1 1 1

The set of all possible input values of the circuit is X={000,001,010,011,100,101,110,111}. The subset of input values X₁, for which circuit S is fault-tolerant, is X₁={000,001,011}. A possible representation of the Boolean function S₁(x) is for example

S ₁(x)=(x ₁ ⊕x ₃)

(x ₁

x ₂

x ₃)  (1.1)

wherein ⊕ stands for the XOR or anti-valence operation,

for the OR operation (disjunction) and

for the AND operation (conjunction). Equation (1.1) is checked most simply by inserting all 8 values for (x₁x₂x₃)εX. The input values 000, 001 and 011, which belong to X₁, are marked in table 1 with + in the column headed X₁. In table 2, in addition to the values of function S₁(x) of table 1, the values of functions s₂(x) and s₃(x) have been entered, which are realised by circuits s₂ and s₃.

TABLE 2 x₁ x₂ x₃ S₁ (x) X₁ s₂ (x) s₃ (x) X\X₁ X₂ 0 0 0 0 + 0 0 0 0 1 1 + 1 1 0 1 0 0 0 1 + + 0 1 1 1 + 1 1 1 0 0 1 0 1 + + 1 0 1 0 0 1 + + 1 1 0 1 0 1 + + 1 1 1 1 0 1 + +

The input values belonging to the subsets X\X₁ and X₂, respectively, are marked by an + in the columns headed X\X₁ and X₂ respectively. Table 2 shows that the subsets X\X₁ and X₂ are the same. Possible representations of the Boolean functions s₂(x) and s₃(x) are

s ₂(x)= x ₁ x ₃  (1.2)

s ₃(x)=x ₁

x ₂

x ₃  (1.3)

FIG. 4 shows an embodiment of the circuit arrangement according to FIG. 3 with circuits S=S₁, s₂ and s₃, which realise the functions S₁(x), s₂(x) and s₃(x) described by table 2 and by equations (1.1), (1.2) and (1.3).

The circuit arrangement of FIG. 4 consists of circuits S₁ 41, s₂ 42, s₃ 43 and a voter V 49. Circuit S₁ consists of XOR gate 44, AND gate 45 and OR gate 46. Circuit s₂ 42 consists of AND gate 47 and circuit s₃ 43 consists of OR gate 48. The input line carrying input signal x₁ is connected with the first input of XOR gate 44, the first input of AND gate 45, the first input of OR gate 48 and in a negated manner with the first input of AND gate 47. The input line carrying input signal x₂ is connected with the second input of AND gate 45 and with the second input of OR gate 48. The input line carrying input signal x₃ is connected with the second input of XOR gate 44, the third input of AND gate 45, the second input of AND gate 47 and the third input of OR gate 48. The output of XOR gate 44 is connected with the first input of OR gate 46, the second input of which is connected with the output of AND gate 45 and whose output carrying the signal y₁ is fed into the first input of voter V 49. The output of AND gate 47 carrying the value y₂ is connected with the second input of voter V 49. The output OR gate 48 carrying the signal y₃ is fed into the third input of voter V 49. Voter V 49 outputs the signal y at its output.

The circuit S₁ 41 comprises 3 gates: XOR 44, AND 45 and OR 46, whilst circuit s₂ 42 comprises only AND gate 47 and circuit s₃ 43 comprises only OR gate 48. It is clear that circuits s₂ and s₃ require less expenditure for their realisation than S₁. If for example input value (x₁, x₂, x₃)=001 from the subset X₁ is input, gates 46, 47 and 48, in a fault-free case, respectively output the value y₁=y₂=y₃=1, which voter V 49 uses for performing the majority decision y=1.

Let it be assumed that a stuck-at-0 fault is present at the first input of OR gate 46, which is connected with the output of XOR gate 44. The value at this input then is constantly 0, and for an input of 001 from X₁ the OR gate 46 and thus the circuit S₁ 41 outputs the erroneous value 0. Since circuits s₂ 42 and s₃ 43 are not affected by this fault, they continue to output the value 1 so that voter V 49 forms the correct output value y=1 from its input value (y₁y₂y₃)=011, whereby the error due to this fault is tolerated.

Similarly errors or faults in the partial circuits s₂ or s₃ are tolerated when inputting values xεX₁. A fault at the output of circuit s₂ 42 may thus be caused in that at the second input of AND gate 47, which carries the signal x₃, a stuck-at-0 fault occurs resulting in this input always carrying the value 0. When inputting 001 the output of AND gate 47 then shows the value 0 instead of the correct value 1 and circuit s₂ 42 outputs the faulty value 0. Circuits S₁ 41 and s₃ 43, however, output the respectively correct value of 1, resulting in the voter V 49 generating the correct result y=1.

For the same fault, given an input of 011, a value of 1 is present at the output of XOR gate 44 and a value of 0 is present at the output of AND gate 45, so that the OR gate 46 and thus the circuit S₁ 41 outputs a value of 1. The output of OR gate 48 and thus the output of circuit s₃ 43 also show a value of 1. The output of AND gate 47 and thus the output of circuit s₂ 42 shows a value of 0. The voter V 49 forms the majority signal 1 from the signals 101 present at its inputs, and the error or fault of circuit s₂ 42 is tolerated for an input of 011 from the subset X₁. Thus the general result is that each error due to a fault affecting only one of partial circuits S₁, s₂ or s₃ is tolerated for an input of an arbitrary xεX₁ by the circuit according to FIG. 4.

In a further embodiment a combinational circuit S with 3 inputs x₁, x₂, x₃ and A₁=3 binary outputs y₁, y₂, y₃ shall now be considered. The combinational circuit S realises the three Boolean functions S₁ ¹(x)=y₁, S₁ ²(x)=y₂, S₁ ³(x)=y₃ the table of values of which are shown in table 3. Thus x=(x₁,x₂,x₃), and the three Boolean functions S₁ ¹(x), S₁ ²(x), S₁ ³(x) are combined to form S₁(x)=(S₁ ¹(x), S₁ ²(x),S₁ ³(x)). The first output of circuit S, which implements function S₁ ¹(x), is supplemented by two further outputs of additional circuits s₂ ¹ and s₃ ¹, which implement the Boolean functions s₂ ¹(x) und s₃ ¹(x). The second output of circuit S, which implements the function S₁ ²(x), is supplemented by two further outputs of additional circuits s₂ ² und s₃ ², which implement the Boolean functions s₂ ²(x) and s₃ ²(x). The third output of circuit S, which implements the function S₁ ³(x), is not supplemented by further outputs, since no fault tolerance is required for this circuit output. The first circuit component thus realises the Boolean functions S₁ ¹(x), S₁ ²(x) and S₁ ³(x) at their A₁=3 binary outputs. The second circuit component realizes the Boolean functions s₂ ¹(x) und s₂ ²(x) at their a₁=2 binary outputs, whilst the third circuit component realizes the Boolean functions s₃ ¹(x) and s₃ ²(x) at their a₁=2 binary outputs. The fault tolerance here is realised only for the output values of word width a₁=2, which are output at the first two binary outputs of all A₁=3 circuit outputs of circuit component S₁. The second and third circuit components s₂ and s₃ therefore comprise only a₁=2 binary circuit outputs, respectively.

For X₁={011}, i.e. for the input value 011, a circuit arrangement according to the invention is to be determined, which is fault-tolerant for the first two outputs y₁ und y₂. No fault-tolerance is provided for input values X\X₁={000,001,010,100,101,110,111}. Independently of any input no fault-tolerance may be required for output y₃.

TABLE 3 x₁ x₂ x₃ S₁ ¹ (x) = y₁ S₁ ² (x) = y₂ S₁ ³ (x) = y₃ X₁ 0 0 0 0 1 0 0 0 1 0 0 1 0 1 0 1 1 1 0 1 1 0 1 0 + 1 0 0 1 0 0 1 0 1 0 0 1 1 1 0 0 0 1 1 1 1 1 1 0

Table 4 shows a truth table for the functions S₁ ¹(x), S₁ ²(x), S₁ ³(x), s₂ ¹(x), s₂ ²(x), s₃ ¹(x), s₃ ²(x), which meets the fault-tolerance requirements for input value 011. Table 4 reveals that the following applies to x=(011)εX₁={011}:

S ₁ ¹(011)=s ₂ ¹(011)=s ₃ ¹(011)=0

S ₁ ²(011)=s ₂ ²(011)=s ₃ ²(011)=1.

In other respects the following applies to all xε(X\X₁),

[S ₁ ¹(x)=s ₂ ¹(x)] or [S ₁ ¹(x)=s ₃ ¹(x)]

and

[S ₁ ²(x)=s ₂ ²(x)] or [S ₁ ²(x)=s ₃ ²(x)].

TABLE 4 x₁ x₂ x₃ S₁ ¹ (x) S₁ ² (x) S₁ ³ (x) s₂ ¹ (x) s₂ ² (x) s₃ ¹ (x) s₃ ² (x) X₁ 0 0 0 0 1 0 1 0 0 1 0 0 1 0 0 1 1 0 0 1 0 1 0 1 1 1 1 0 0 1 0 1 1 0 1 0 0 1 0 1 + 1 0 0 1 0 0 1 0 0 1 1 0 1 0 0 1 1 0 0 1 1 1 0 0 0 1 1 0 0 1 1 1 1 1 0 0 1 0 0 1

At least one of values s₂ ¹(x) or s₃ ¹(x) matches S₁ ¹(x) and at least one of values s₂ ²(x) or s₃ ²(x) matches S₁ ²(x), which can easily be checked using table 4. Again, it is very easy to check by repeating the calculation or by using a commonly used synthesis tool that

y ₁ =S ₁ ¹(x)= x ₁ x ₂ x ₃

x ₁( x ₂ ⊕x ₃ )

y ₂ =S ₁ ²(x)= x ₁ (x ₂

x ₃ )

y ₃ =S ₁ ³(x)=x ₂ ⊕x ₃

s ₂ ¹(x)= x ₁ x ₂ x ₃

s ₂ ²(x)= x ₁ x ₂ x ₃

s ₃ ¹(x)=0

s ₃ ²(x)=1

are possible realisations of the functions shown in table 4.

FIG. 5 shows a corresponding circuit arrangement which is fault-tolerant especially for input value x₁x₂x₃=011 at the first two outputs y₁ and y₂. The circuit S for implementing the Boolean functions S₁ ¹(x), S₁ ²(x) and S₁ ³(x) comprises gates 51, 52, 53, 54, 55, 56 and 57. The circuit for implementing the Boolean functions s₂ ¹(x) and s₂ ²(x) comprises gates 58 und 59. The circuit for implementing the Boolean functions s₂ ¹(x) und s₃ ²(x) comprises gates 510 und 511. The output of gate 510 still shows the value 0 and the output of gate 511 still shows the value 1. It can be recognised that hardware expenditure for realising the functions s₂ ¹, s₂ ² and s₃ ¹, s₃ ² is less than the expenditure for realising the functions S₁ ¹ and S₂ ¹.

The input line carrying the binary signal x₁ is fed in non-negated form into the first input of AND gate 53, AND gate 510 and OR gate 511, respectively. In negated form x₁ is fed into the first input of AND gate 52, AND gate 56, NAND gate 58, AND gate 59, respectively, and into the second input of AND gate 510 and OR gate 511, respectively. The input line carrying the binary signal x₂ is fed into the first input of XNOR gate 51, into the second input of AND gate 52, into the first input of OR gate 55, into the first input of XOR gate 57, into the second input of NAND gate 58 and into the second input of AND gate 59. The line carrying the binary signal x₃ is connected in non-negated form with the second input of XNOR gate 51, the second input of XOR gate 57, the third input of NAND gate 58, the third input of AND gate 59 and connected in negated form with the third input of AND gate 52 and the second input of OR gate 55.

The output of XNOR gate 51 is connected with the second input of AND gate 53, whose output is fed into the first input of an OR gate 54.

The output of AND gate 52 is connected with the second input of OR gate 54, whose output carries the value S₁ ¹(x) and is fed into the first input of voter V₁ 512.

The output of OR gate 55 is connected with the second input of AND gate 56, whose output carries the signal S₁ ²(x) and is connected with the first input of voter V₂ 513.

The output of XOR gate 57 carries the value y₃(x) which is output by circuit S. The output of NAND gate 58 carries the signal s₂ ¹(x) and is connected with the second input of voter V₁ 512, whilst the output of AND gate 59 carrying the signal s₂ ²(x) is connected with the second input of voter V₂ 513.

The output of AND gate 510 carrying the here constant signal s₃ ¹(x), is connected with the third input of voter V₁ 512, whilst the output of OR gate 511 carrying the here constant signal s₃ ²(x) is connected with the third input of voter V₂ 513. The voter V₁ 512 outputs, at its output, the output value y₁(x), whilst the voter V₂ 513 outputs the output value y₂(x) at its output. The voters V₁ 512 and V₂ 513, which perform a bit-by-bit majority decision, are combined in FIG. 5 to form one voter V 514. The output of XOR gate 57 is an output of the circuit carrying the output signal y₃(x). This output is not implemented so as to be fault-tolerant.

The outputs of voters V₁ 512 and V₂ 513 carrying the signals y₁(x) and y₂(x) respectively are the circuit outputs which are implemented so as to be fault-tolerant. Voters V₁ 512 and V₂ 513 performing a majority decision across the three inputs present at their inputs are combined to form one voter V 514 with 6 inputs and 2 outputs. Voter V₁ 512 performs a majority decision across its values S₁ ¹(x), s₂ ¹(x), s₃ ¹(x) present at its inputs and voter V₂ 513 performs a majority decision across its values S₁ ²(x), s₂ ²(x), s₃ ²(x) present at its inputs.

The circuit of FIG. 5 is fault-tolerant at outputs y₁ and y₂ for input value 011. If this input is present at the inputs, this results in S₁ ¹(0,1,1)=0, s₂ ¹(0,1,1)=0, s₃ ¹(0,1,1)=0 and S₁ ²(0,1,1)=1, s₂ ²(0,1,1)=1, s₃ ²(0,1,1)=1. If in case of a fault one of values S₁ ¹(0,1,1), s₂ ¹(0,1,1) or s₃ ¹(0,1,1) is in error, such an error is tolerated due to the majority decision of voter V₁ 512. Similarly: if in case of a fault only one of values S₁ ²(0,1,1), s₂ ²(0,1,1), s₃ ²(0,1,1) is in error, this error is tolerated by V₂ 513.

For an input of 100 the result in a fault-free case is S₁ ¹(1,0,0)=1, s₂ ¹(1,0,0)=1 and s₃ ¹(1,0,0)=0, resulting in voter V₁ 512 generating the correct value y₁(1,1,0)=1. Now, if a stuck-at-0 fault is present at the first input of AND gate 53, which carries the value x₁=1, the first and second inputs of OR gate 54 show the value 0, resulting in this gate outputting the faulty value 0 at its output, with the result that voter V₁ 512 processes the input 0,1,0 into 0. For an input of (1,0,0)εX₂ the fault is not tolerated. Output y₃ formed by the output of XOR gate 57 is not implemented so as to be fault-tolerant.

Analogously this leads to the circuit of FIG. 5 being fault-tolerant for an input of (0,1,1)εX₁ at its second output, which carries the signal y₂(x), since as already mentioned, S₁ ²(0,1,1)=1, s₂ ²(0,1,1)=1 and s₃ ²(0,1,1)=1.

FIG. 6 shows a further design of a combinational circuit arrangement. The combinational circuit S=S₁ 61 is supplemented by two combinational circuits s₂ 62 and s₃ 63. Combinational circuit S₁ 61 is the first combinational circuit component, combinational circuit s₂ 62 is the second combinational circuit component and combinational circuit s₃ 63 is the third combinational circuit component of the circuit arrangement according to the invention. The set of possible input values of circuit S is designated with X. The set of input values for which the circuit arrangement of FIG. 6 is fault-tolerant is designated with X₁. X₁ is a true or proper subset of X. The circuit arrangement is defined such that

S(x)=S ₁(x)=s ₂(x)=s ₃(x) for xεX ₁ with X ₁ ⊂X

and

(S ₁(x)=s ₂(x)) or (S ₁(x)=s ₃(x)) for xεX

wherein there exists a non-empty subset X₂ ⊂(X\X₁) so that

s ₁(x)≠s ₂(x) for xεX ₂.

Also present are a combinational circuit σ66 for realising a Boolean function σ(x) and a multiplexer MUX 65. The Boolean function σ(x) is defined as

${\sigma (x)} = \left\{ \begin{matrix} {{b\mspace{14mu} {for}\mspace{14mu} x} \in X_{1}} \\ {{b\mspace{14mu} {for}\mspace{14mu} x} \in X_{2}} \\ {{arbitrary}\mspace{14mu} {in}\mspace{14mu} {all}\mspace{14mu} {other}\mspace{14mu} {cases}} \end{matrix} \right.$

In this formula b is a fixed value which can be fixed to be 0 or 1. If xε(X\(X₁∪X₂)), then σ(x) can be specified arbitrary. An expert would define σ(x) for xε(X\(X₁∪X₂)) depending on the requirement by a CAD tool in such a way that circuit σ occupies as small an area as possible for implementing the Boolean function σ(x). The output of combinational circuit S₁ 61 carrying the signal S₁(x) is fed into the first input of a voter V 64, at the second input of which is connected the output of combinational circuit s₂ 62 carrying the signal s₂(x) and at the third input of which is connected the output of combinational circuit s₃ 63 carrying the signal s₃(x). The output of voter V 64 carrying the signal m(x), which represents the majority of values of S₁(x), s₂(x) and s₃(x) is connected with a first data input of multiplexer MUX 65, into the second data input of which is fed the output of combinational circuit S₁ 61 and whose data output carries the signal y(x). The control input of multiplexer MUX 65 is connected with the output of combinational circuit σ66 carrying the control signal σ(x).

In the following it is assumed that b=1 for the description of the mode of operation of the circuit arrangement of FIG. 6, in order to simplify the description. Analogously a description for b=0 is also possible. If xεX₁, then σ(x)=1 and the multiplexer MUX 65 connects its corresponding 1-input with its output so that y(x)=m(x). Moreover S₁(x)=s₂(x)=s₃(x) is applicable and voter V 64 determines the value m(x)=S₁(x)=s₂(x)=s₃(x), which is fed to output y(x).

Individual faults of individual circuit components will now be considered. If only one of output values S₁(x), s₂(x) or s₃(x) for xεX₁ is faulty, this faulty value will be corrected by the majority decision of the voter and the correct value y(x) is output. If the control value σ(x) generated by circuit σ66 is equal to 0 which is faulty, the correct value S₁(x) is forwarded to the output of multiplexer MUX 65 and y(x)=S(x) is again correct. If xεX₂, then σ(x)=0 and the output of circuit S₁ 61 is forwarded to the output of multiplexer 65, so that y(x)=S₁(x). Now if output value S₁(x) is faulty, the faulty value is sent to the output of the circuit arrangement. This is the only case, in which a fault at one of the circuit components S 61, s₂ 62, s₃ 63, σ66 results in an error at the output value y(x). Further individual faults of the listed circuit components do not have any effect.

Any faults in voter 64 and in multiplexer 65 have nothing to do with the subject of the patent claims and are therefore not addressed here.

For example, if a fault-tolerance of the combinational circuit S with respect to a set of technical faults {φ₁, . . . , φ₅}=Φ shall be achieved, the set X₁ has to be selected such, that X₁ contains all input values, for which an arbitrary fault φεΦ impacts upon the output behaviours of S₁.

As a typical example for determining the Boolean functions σ(x), s₂(x), s₃(x) a combinational circuit S with S=S₁(x)=S₁(x₁,x₂,x₃,x₄)=x₂x₃

x₂(x₁⊕x₄)

x₁ x₂ x₃x₄ shall be considered, which shall be fault-tolerant for the set of input values X₁={0000,0010,0111,1110,1111}. The first combinational circuit component with A₁=a₁=1 realises the Boolean function S₁(x), the second combinational circuit component realises the Boolean function s₂(x) and the third combinational circuit component realises the Boolean function s₃(x).

Table 5, in the first four columns, shows the input values for x₁, x₂, x₃, x₄ and in the fifth column the functional values of the Boolean function S₁(x). In the sixth column those lines are marked with +, for whose input assignments the circuit arrangement according to the invention shall be fault-tolerant. These are the first, third, eighth, fifteenth and sixteenth line. For the input assignments 0000, 0010, 0111, 1110 and 1111 corresponding to these lines the values of the Boolean functions s₂(x) and s₃(x) are identical and they also match with S₁(x), so that

S ₁(x)=s ₂(x)=s ₃(x) for xεX ₁.

Next the still-to-be-determined functional values of the Boolean function s₂(x) can be arbitrarily fixed in principle. In order to simplify realisation an expert would optimise s₂(x) with the functional values fixed for xεX₁, by applying a commonly used synthesis tool. To this end he would, for example, select all still undefined functional values of s₂(x) as don't-care and thus optimise the given partially defined Boolean function, as is common.

For example, let it be assumed that s₂(x) is defined as s₂(x)=x₂(x₃

x₄). For this function the functional values are entered in column 8 of table 5. It will now be described how the Boolean function s₃(x) can be defined.

xεX₁ is defined as s₃(x)=S₁(x), as is the function s₂(x). Thus: s₃(0000)=S₁(0000)=0, s₃(0010)=S₁(0010)=0, s₃(0111)=S₁(0111)=1, s₃(1110)=S₁(1110)=1, s₃(1111)=S₁(1111)=1. For the input values x, which are defined as s₂(x)≠S₁(x), s₃(x)=S₁(x) is set. Table 5 shows that the inequality s₂(x)≠S₁(x) for xε{1011,1100,1101} is satisfied. Thus: s₃(1011)=S₁(1011)=1, s₃(1100)=S₁(1100)=1 and s₃(1101)=S₁(1101)=0. The still-to-be-fixed values s₃(x) may again be arbitrarily fixed at random. An expert would set all of the still-to-be-fixed values of s₃(x) to be don't-care. In a concrete case these are the values for s₃(0001), s₃(0011), s₃(0100), s₃(0101), s₃(0110), s₃(1000), s₃(1001), s₃(1010) for which don't-care values can be set. Then he would optimise the described partially defined Boolean function using a commonly used CAD tool for example, as is common when circuits are designed.

TABLE 5 s₃ (x) = x ₁x₂

s₂ (x) = x₁(x₃

σ(x) = x₁ x₂ x₃ x₄ S₁(x) X₁ X₂ x₂(x₃

 x₄) x₂ x ₄) x₁x ₂

 x₂x₃ 0 0 0 0 0 + 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 + 0 0 1 0 0 1 1 0 0 0 1 0 1 0 0 0 + 0 1 0 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 + 1 1 1 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 1 0 0 + 0 1 0 1 0 1 1 1 + 0 1 0 1 1 0 0 1 + 0 1 0 1 1 0 1 0 + 1 0 0 1 1 1 0 1 + 1 1 1 1 1 1 1 1 + 1 1 1

For example, let it be assumed that s₃(x) was determined to be s₃(x)= x₁ x₂

x₁(x₃

x₂ x₄ ). The functional values of this function s₃(x) have been entered into column 9 of table 5.

There now follows a description, how function σ is defined, which is illustrated in column 10 of table 5. In the lines marked with + in the column headed X₁, the value of σ(x) equals 1. These are the first, third, eighth, fifteenth and sixteenth lines, which are allocated to the assignments 0000, 0010, 0111, 1110 and 1111. In the lines in which s₂(x) and s₃(x) are not equal, the value of σ(x) equals 0. These are the fifth, eleventh, twelfth, thirteenth and fourteenth lines, which are allocated to the assignments 0100, 1010, 1011, 1100 and 1101. All still-to-be-fixed values are again to be selected as arbitrary values or don't-care. As is common in circuit design, a CAD tool can again be used to define the function σ, which matches the values already fixed in column 10. For example, let it be assumed that σ has been defined to be σ(x)= x₁x₂

x₂x₃. The functional values of this function have been entered in column 10 of table 5.

As a result, the following is true

If xεX₁, then follows σ(x)=1 (lines 1, 3, 8, 15, 16)

If σ(x)=1, then follows S₁(x)=s₂(x)=s₃(x) (lines 1, 2, 3, 4, 7, 8, 15, 16)

If s₂(x)≠s₃(x), then follows σ(x)=0 (lines 5, 11, 12, 13, 14)

If σ(x)=0, then follows s₂(x)=s₃(x)=S₁(x) (e.g. line 9) or s₂(x)≠s₃(x) (e.g. line 5)

The set of input values X₂, for which s₂(x)≠s₃(x), is marked with a + in column 7 headed X₂. They form the set {0100,1010,1011,1100,1101}=X₂. Furthermore the following applies:

(X\X ₁)={0001,0011,0100,0101,0110,1000,1001,1010,1011,1100,1101},

(X\X ₁)⊃X ₂,

X ₂={0100,1010,1011,1100,1101}

where X₂ is a proper subset of X\X₁. It should not be difficult for an expert to implement the corresponding Boolean functions as combinational circuits.

FIG. 7 shows a further design of a circuit arrangement for realising a fault-tolerant combinational circuit S, which realises a particularly effective fault-tolerance. In FIG. 7 the combinational circuit S is realised three times as S₁ 71, S₂ 72 and S₃ 73 with identical functions, resulting in

S(x)=S ₁(x)=S ₂(x)=S ₃(x) for xεX

applying to all xεX from the set of possible input values.

X₁ is the partial quantity of input values, for which a particularly high fault-tolerance shall be achieved. The three circuits S₁ 71, S₂ 72 and S₃ 73 are supplemented by the two combinational circuits s₄ 74 and s₅ 75, resulting in

S(x)=s ₄(x)=s ₅(x) for xεX ₁

(S(x)=s ₄(x)) or (S(x)=s ₅(x)) for xεX

wherein again a non-empty partial quantity X₂ ⊂(X\X₁) exists, resulting in

s ₄(x)≠s ₅(x) for xεX ₂

The same input value x is present at each of the combinational circuits S₁ 71, S₂ 72, S₃ 73, s₄ 74 and s₅ 75. For i=1, 2, 3 the output of combinational circuit S, carrying the output signal S_(i)(x) is fed into the i-th input of voter V 76. The output of combinational circuit s₄ carrying the output signal s₄(x) is fed into the fourth input of voter V 76, whilst the output of combinational circuit s₅ carrying the output signal s₅(x) is connected with the fifth input of voter V 76. The voter V 76 with 5 inputs outputs the value m(x)=y(x) at its output, wherein m(x) is the value, which most frequently occurs at the 5 inputs of voter V 76.

If xεX₁, in a fault-free case, 5 identical values are present at the input of voter V 76 and up to two faulty values are tolerated by the circuit in FIG. 7 as output of S₁ 71, S₂ 72, S₃ 73, s₄ 74 and s₅ 75. If xεX₂, in a fault-free case, 4 identical values are present at the input of voter V 76 as output of S₁ 71, S₂ 72, S₃ 73, s₄ 74 and s₅ 75 and one faulty value is tolerated by the circuit in FIG. 7.

For xεX₁ the circuit arrangement of FIG. 7 has the fault-tolerance characteristics of a fault-tolerant system, wherein the original system is five times implicated, and for xε(X\X₁) of at least of a system where the original system is triplicated, wherein expenditure is less than for the system which is five times implicated.

The first combinational circuit component S₁ 71 realises the function S₁(x), the second combinational circuit component s₄ 74 realises the function a₄(x) and the third combinational circuit component s₅ 75 realises the function s₅(x). These circuit components are supplemented by two further combinational circuit components S₂ 72 and S₃ 73, which also realise the same function, respectively, as the first circuit component.

FIG. 8 shows a further embodiment of a fault-tolerant circuit arrangement. The circuits S₁ 81, s₂ 82 and s₃ 83 are identical with circuits S₁ 31, s₂ 32 and s₃ 33 of FIG. 3. In FIG. 8 a voter is present three times as voter V₁ 84, V₂ 85 and V₃ 86.

The output of combinational circuit S₁(x) carrying the signal S₁(x) is simultaneously fed into the respectively first inputs of voters V₁ 84, V₂ 85 and V₃ 86. The output of combinational circuit s₂ 82 carrying the signal s₂(x) is simultaneously fed into the respectively second inputs of voters V₁ 84, V₂ 85 and V₃ 86, whilst the output of circuit s₃ 83 carrying the signal s₃(x) is connected with the respectively third inputs of voters V₁ 84, V₂ 85 and V₃ 86. The voters V₁ 84, V₂ 85 and V₃ 86 output the majority signals m₁(x), m₂(x) and m₃(x) respectively. If one voter is faulty, most of the majority signals are correct.

FIG. 9 shows a further fault-tolerant circuit arrangement. The circuit arrangement of FIG. 9 comprises a circuit S 96, which is fault-tolerant with respect to the input set X₁ and which has a circuit T 95 arranged upstream of it. The circuit S 96 comprises the circuits S₁ 91, s₂ 92 and s₃ 93 and a voter V 94, as described with reference to FIG. 3.

The circuit T 95 processes input values u from a quantity U of inputs into output values T(u), which form the set of output values W of circuit T 95. k, k≧2 stands for the word width of the output of circuit T 95, which is simultaneously connected with the m-bit wide inputs of circuits S₁ 91, s₂ 92 and s₃ 93, wherein m=k. The set of possible inputs in principle of circuit S 96 is X={0,1}^(k), i.e. the set of all k-digit binary vectors.

If the circuit T 95 is designed in such a way that W is a proper subset of X, then X₁⊂W is selected in FIG. 9, and the circuit S is fault-tolerant for all input values from the set X₁, wherein X₁ is a proper subset of W.

The output of circuit T 95 is connected simultaneously with the inputs of circuits S₁ 91, s₂ 92 and s₃ 93. The output of circuit S₁ 91 is connected with the first input of a voter V 94 with three inputs. The output of circuit s₂ 92 is connected with the second input of voter V 94 and the output of circuit s₃ 93 is connected with the third input of voter V 94, which at its output outputs a majority signal m(x).

A circuit T 101, which processes input values u=u₁u₂ε{00,01,10,11} into output values T(u)=T₁(u)T₂(u)=x₁x₂ε{00,01,11}ε{00,01,10,11}, is shown in FIG. 10. The set {00,01,11} of output values of circuit T 101 is a proper subset of the set X={0,1}²={00,01,10,11} of all possible input values of circuit S 104. It is thus possible, to select X₁ as a subset of W={00,01,11}, for example as X₁={00, 01}, for which the circuit S 104 is a fault-tolerant circuit according to the invention.

The circuit T 101 comprises an AND gate 102 and an OR gate 103, into which the input values u=u₁u₂ε{00,01,10,11} are input and which are processed by the circuit T 101 into the output values T(u)=T₁(u)T₂(u)ε{00,01,11}. The input of circuit T 101 carrying the first component u₁ of the input value u is connected with the respectively first input of gates AND102 and OR103, into whose respective second input is fed the input of circuit T 101 carrying the second component u₂ of input value u. The AND gate 102 outputs the first component T₁(u) and the OR gate 103 outputs the second component T₂(u) of output value T(u).

The features of the invention disclosed in the above description, in the claims and in the drawing can be important both individually and in any given combination to the implementation of the invention in its various embodiments. 

1. An electronic circuit arrangement for processing binary input values xεX of word width n (n>1), comprising: a first combinational circuit component configured to process the binary input values x to form a first binary output value of word width a₁ (a₁≧1) and to provide the first binary output value at the output of the first combinational circuit component, the output of the first combinational circuit component being provided with a number of binary outputs A₁ (A₁>1), wherein A₁≧a₁, a second combinational circuit component configured to process the binary input values x to form a second binary output value, a third combinational circuit component configured to process the binary input values x to form a third binary output value, and a majority voter element, the input of which, for receiving the respective binary input values, is connected with the outputs of the first, second and third combinational circuit components, the majority voter element being configured to provide a majority signal at its output in dependence on the received binary output values, wherein the second and third combinational circuit components are configured, as regards faults during processing of the binary input values x in the first combinatory circuit component, to process, for the first binary output value of word width a₁, binary input values of a true non-empty subset X₁ of the set of binary input values X in a fault-tolerant manner and binary input values of a further non-empty subset X₂ of the set of binary input values X in a non-fault-tolerant manner, the further non-empty partial quantity X₂ being different from the true non-empty subset X₁.
 2. Circuit arrangement according to claim 1, wherein the second and third combinational circuit components are designed to incorporate the following features: in a fault-free case the second binary output value of the second combinational circuit component and the third binary output value of the third combinational circuit component are equal to the first binary output value of the first combinational circuit component, for all binary input values of the non-empty proper subset X₁ for all binary input values from the further non-empty subset X₂ the second binary output value of the second combinational circuit component and the third binary output value of third combinational circuit component are non-equal, and for all binary input values of the subset X₁ the following is true for each bit of the first combinational binary output value of word width a1: at least the second binary output value of the second combinational circuit arrangement or at least the third binary output value of the third combinational circuit component is equal to the first binary output value of the first combinational circuit component.
 3. Circuit arrangement according to claim 1, wherein the second combinational circuit component is configured to process the binary input values x such that the second binary output value is equal to the first binary output value.
 4. Circuit arrangement according to claim 1, wherein further combinational circuit components are configured to process the binary input values x to form the first binary output value, and the output of which is respectively connected to an input of the majority voter element.
 5. Circuit arrangement according to claim 1, comprising further majority voter elements the input of which, for receiving the respective binary output value, is connected with the output of all combinational circuit components and which are respectively configured, depending upon the received binary output values, to provide a majority signal at their output.
 6. Circuit arrangement according to claim 1, wherein the respective input of all combinational circuit components is serial-connected with an output of a further circuit component, wherein the further circuit component is configured to process binary input values uεU to form binary output values W which, at least partially are different from the binary input values xεX, wherein X₁⊂W.
 7. Circuit arrangement according to claim 1, further comprising: a further combinational circuit component configured to process the binary input values x to form binary control signals, and a multiplexer element, wherein the output of the further combinational circuit component carrying the binary control signals is connected with the control input of the multiplexer element, a first data input of the multiplexer element is connected to the output of the first combinational circuit component, and a second data input of the multiplexer element is connected with the output of the majority voter element.
 8. Circuit arrangement according to claim 1, wherein the binary input values of non-empty subset X₁ to form a subset of binary input values, so that for a set Φ of faults φ₁, . . . , φ_(k) occurring in the first circuit component, the following is true: S(x)≠S(φ,x) for xεX₁, wherein s(φ,x) is the binary output value of the first combinational circuit component, if the fault φεΦ is present and the binary input value x is input.
 9. Circuit arrangement according to claim 1, wherein X₂=(X\X₁).
 10. Circuit arrangement according to claim 1, wherein the binary output value of the second circuit component to be 1 and for the binary output value of the third combinational circuit component to be 0 for the binary input values from the further non-empty subset X₂. 